Stack packages using reconstituted wafers

ABSTRACT

A stacked microelectronic unit is provided which has a top surface and a bottom surface remote from the top surface and a plurality of vertically stacked microelectronic elements therein, including at least one microelectronic element having a front face adjacent to the top surface and a rear face oriented towards the bottom surface. Each of the microelectronic elements has traces extending from contacts at the front face beyond edges of the microelectronic element. A dielectric layer contacts edges of the microelectronic elements and underlies the rear face of the at least one microelectronic element. Leads are connected to the traces extending along the dielectric layer. Unit contacts, exposed at the top surface, are connected to the leads.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a divisional of U.S. patent application Ser.No. 12/671,993 filed Jul. 16, 2010, which is a national phase entryunder 35 U.S.C. §371 of International Application No. PCT/US2008/009353filed Aug. 1, 2008, designating the United States, the disclosures ofwhich are incorporated herein by reference. Said internationalapplication claims the benefit of U.S. Provisional Application No.60/963,209 filed Aug. 3, 2007, the disclosure of which is incorporatedherein by reference.

BACKGROUND ART

The subject matter of the present application relates to microelectronicpackages, or assemblies, comprised of stacked microelectronic elementsand to methods of fabricating them, for example, by processing appliedsimultaneously to a plurality of microelectronic elements arranged in anarray.

Microelectronic elements, such as semiconductor chips, are flat bodieswith contacts disposed on the front surface that are connected to theinternal electrical circuitry of the element itself. Microelectronicelements are typically packaged with substrates to form microelectronicpackages, or assemblies, having terminals that are electricallyconnected to the element's contacts. The package or assembly may then beconnected to test equipment to determine whether the packaged deviceconforms to a desired performance standard. Once tested, the package maybe connected to a larger circuit, e.g., a circuit in an electronicproduct such as a computer or a cell phone.

Microelectronic packages or assemblies also include wafer levelpackages, which can be formed by wafer level processing appliedsimultaneously to a plurality of microelectronic elements, e.g.,semiconductor die while the die are still attached together in form of awafer or portion of a wafer. After subjecting the wafer to a number ofprocess steps to form package structure thereon, the wafer and thepackage structure are then diced to free the individual die. Wafer levelprocessing may provide a cost savings advantage. Furthermore, thepackage footprint can be identical to the die size, resulting in veryefficient utilization of area on a printed circuit board (PCB) to whichthe die will eventually be attached. As a result of these features, diepackaged in this manner are commonly referred to as wafer-level chipscale packages (WLCSP).

In order to save space certain conventional designs have stackedmultiple microelectronic chips or elements within a package or assembly.This allows the package to occupy a surface area on a substrate that isless than the total surface area of all the chips in the stack addedtogether. Development efforts in this technology focus on producingwafer-level assemblies that are reliable, or thin, or testable, or whichare economical to manufacture, or have a combination of suchcharacteristics.

SUMMARY OF THE INVENTION

In accordance with an aspect of the invention, a method is provided forfabricating a stacked microelectronic assembly. In accordance with suchmethod, a first subassembly is formed which includes a plurality ofspaced apart first microelectronic elements having front faces andcontacts exposed at the front faces and rear faces remote from the frontfaces and edges extending between the front and rear faces. The firstmicroelectronic elements can be joined to a carrier layer. A pluralityof traces can extend from the contacts to beyond edges of the firstmicroelectronic elements. A plurality of spaced apart secondmicroelectronic elements can then be attached to the first subassembly,the second microelectronic elements having front faces and contactsexposed at the front faces, rear faces remote from the front faces, andedges extending between the front and rear faces. The rear faces of thesecond microelectronic elements can overlie and be adjacent to the frontfaces of respective ones of the first microelectronic elements. Aplurality of traces can then be formed which extend from the contacts ofthe second microelectronic elements to beyond the edges of the secondmicroelectronic elements. Leads may be formed in at least one openingextending between confronting edges of adjacent ones of the firstmicroelectronic elements and between confronting edges of adjacent onesof the second microelectronic elements. The leads can be connected tothe traces of the first and second microelectronic elements.

In accordance with an aspect of the invention, each of the first andsecond microelectronic elements can have a thickness of less than about50 microns between the front face and the rear face. In one embodiment,at least one of the microelectronic elements includes a flash memory.

In accordance with an aspect of the invention, the stackedmicroelectronic assembly can be severed between edges of adjacent onesof the first and second microelectronic elements into a plurality ofstacked microelectronic units, each unit including at least one firstmicroelectronic element and at least one second microelectronic element.

In accordance with one aspect of the invention, the at least one openingcan include channels which extend between the confronting edges ofadjacent ones of the first and second microelectronic elements.

In accordance with one aspect of the invention, the at least one openingcan include a plurality of spaced apart openings aligned with edges ofthe first and second microelectronic elements. The leads may extendwithin respective individual ones of the spaced apart openings, eachlead being conductively connected with a single one of the traces.

In accordance with an aspect of the invention, a method is provided forfabricating a stacked microelectronic assembly. In accordance with suchmethod, first and second subassemblies can be provided, each subassemblyhaving a front surface and a rear surface remote from the front surface.Each subassembly can include a plurality of spaced apart microelectronicelements having front faces and contacts adjacent to the front surface,rear faces adjacent to the rear surface, and edges extending between thefront and rear faces. A plurality of traces can be formed at the frontsurface of the first subassembly, the traces extending from the contactsof the first subassembly to beyond the edges of the microelectronicelements of the first subassembly. The first and second subassembliescan be joined such that the rear surface of the second subassemblyconfronts the front surface of the first subassembly. A plurality oftraces can be formed at the front surface of the second subassembly. Thetraces may extend from the contacts of the second subassembly to beyondthe edges of the microelectronic elements of the second subassembly.Leads can be formed in at least one opening extending between edges ofadjacent microelectronic elements of the first and second subassemblies.The leads can be connected to the traces of the microelectronic elementsof the first and second subassemblies.

In accordance with an aspect of the invention, each of themicroelectronic elements of the first and second subassemblies has athickness of less than about 50 microns between the front face and therear face.

In accordance with an aspect of the invention, at least one of themicroelectronic elements includes flash memory.

In accordance with an aspect of the invention, the stackedmicroelectronic assembly can be severed between edges of adjacentmicroelectronic elements into a plurality of stacked microelectronicunits, each unit including microelectronic elements from each of thefirst and second subassemblies and leads connected to traces of themicroelectronic elements.

In accordance with an aspect of the invention, the at least one openingcan include channels extending between confronting edges of adjacentmicroelectronic elements.

In accordance with an aspect of the invention, the at least one openingincludes a plurality of spaced apart openings aligned with edges of themicroelectronic element. Leads of each stacked microelectronic unit mayextend within respective individual ones of the spaced apart openings,each lead being conductively connected with a single one of the traces.

In accordance with an aspect of the invention, the front face of a givenmicroelectronic element of the second subassembly can have at least onedimension different from a corresponding dimension of the front face ofa microelectronic element of the first subassembly that the front faceof the given microelectronic element overlies.

In accordance with an aspect of the invention, a front face of a givenmicroelectronic element of the first subassembly can have at least onedimension different from a corresponding dimension of a front face ofanother microelectronic element of the first subassembly.

In accordance with an aspect of the invention, a front face of a givenmicroelectronic element within the stacked assembly can have at leastsubstantially the same dimensions as a front face of anothermicroelectronic element that the given microelectronic element overlieswithin the stacked assembly.

In accordance with an aspect of the invention, each subassembly canfurther include alignment features adjacent to the front surface. Thealignment features and the traces can be elements of the same metallayer exposed at the front surface.

In accordance with an aspect of the invention, the second subassemblycan be joined to the first subassembly such that edges ofmicroelectronic elements of the second subassembly are displaced in alateral direction relative to edges of microelectronic elements of thefirst subassembly in vertical alignment therewith. The at least oneopening can have a sloped wall exposing the traces adjacent to thelaterally displaced edges of the vertically stacked microelectronicelements.

In accordance with such aspect of the invention, the lateral directioncan be a first lateral direction and the edges of each microelectronicelement can include first edges and second edges transverse to the firstedges. In accordance with such aspect, the second subassembly can bejoined to the first subassembly such that second edges ofmicroelectronic elements of the second subassembly are further displacedin a second lateral direction relative to second edges ofmicroelectronic elements of the first subassembly in vertical alignmenttherewith. The second lateral direction can be transverse to the firstlateral direction. A second opening having a sloped wall can be formedwhich exposes second traces adjacent to the second edges. Leads can beformed which are connected to the second traces.

In accordance with an aspect of the invention, a stacked microelectronicunit can be provided which has a top surface and a bottom surface remotefrom the top surface and a plurality of vertically stackedmicroelectronic elements therein. At least one microelectronic elementmay have a front face adjacent to the top surface and a rear faceoriented towards the bottom surface. Each of the microelectronicelements can have traces extending from contacts at the front facebeyond edges of the microelectronic element. A dielectric layer maycontact edges of the microelectronic elements and may underlie the rearface of the at least one microelectronic element. Leads can be connectedto the traces extending along the dielectric layer. Unit contacts,exposed at the top surface, can be connected to the leads.

In accordance with such aspect of the invention, at least some bottomunit contacts can be exposed at the bottom surface, the bottom unitcontacts being connected to the contacts of at least one of themicroelectronic elements.

In accordance with an aspect of the invention, a stacked microelectronicunit can be provided which includes a first microelectronic elementhaving a front face bounded by a first edge and a second edge remotefrom the first edge. A second microelectronic element can have a frontface bounded by a first edge and a second edge remote from the firstedge, and the first edge of the second microelectronic element canoverlie the front face of the first microelectronic element, such thatthe first edge of the first microelectronic element extends beyond thefirst edge of the second microelectronic element. A dielectric layer mayoverlie the first edges of the first and second microelectronicelements. The dielectric layer may define an edge of the stacked unit.Leads can be connected to traces at the front faces of the first andsecond microelectronic elements. The leads can extend along the edge ofthe stacked unit.

In accordance with an aspect of the invention, the first and secondmicroelectronic elements can include third edges oriented in a directiontransverse to the first edges. The third edge of the secondmicroelectronic element can overlie the front face of the firstmicroelectronic element and the third edge of the first microelectronicelement can extend beyond the third edge of the second microelectronicelement. The dielectric layer may define a second edge of the stackedunit overlying the third edges of the microelectronic elements. Thestacked unit may further include second leads extending along the secondedge of the stacked unit.

In accordance with an aspect of the invention, a stacked microelectronicunit can be provided which includes a first microelectronic elementhaving a front face bounded by a first edge and a second edge remotefrom the first edge. A second microelectronic element may have a frontface bounded by a first edge and a second edge remote from the firstedge. The front face of the second microelectronic element can overliethe front face of the first microelectronic element. The front faces ofthe first and second microelectronic elements may differ in at least oneof length along the front faces in a longitudinal direction or in widthalong the front faces in a lateral direction transverse to thelongitudinal direction. A dielectric layer can overlie the first edgesof the first and second microelectronic elements. The dielectric layermay define an edge of the stacked unit. Leads can be connected to tracesat front faces of the microelectronic elements and the leads may extendalong the edge of the stacked unit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view illustrating a wafer or portion of a waferincluding a plurality of microelectronic elements attached together atedges.

FIG. 1B is a corresponding sectional view through line 1B-1B of FIG. 1A.

FIG. 2A is a sectional view of a wafer or portion of a wafer in apreliminary stage in a fabrication method in accordance with anembodiment of the invention.

FIG. 2B is a sectional view of a wafer or portion of a wafer in a stagesubsequent to the stage illustrated in FIG. 2A in a fabrication methodaccording to an embodiment of the invention.

FIG. 2C is a sectional view illustrating a stage in a fabrication methodaccording to an embodiment of the invention subsequent to the stageillustrated in FIG. 2B.

FIG. 3 is a sectional view illustrating a stage in a fabrication methodaccording to an embodiment of the invention subsequent to the stageillustrated in FIG. 2C.

FIG. 4A is a fragmentary plan view illustrating a stage in a fabricationmethod according to an embodiment of the invention subsequent to thestage illustrated in FIG. 3.

FIG. 4B is a corresponding sectional view through line 4B-4B of FIG. 4A.

FIG. 4C is a corresponding sectional view through line 4C-4C of FIG. 4A.

FIG. 5 is a sectional view illustrating a stage in a fabrication methodaccording to an embodiment of the invention subsequent to the stageillustrated in FIGS. 4A-C.

FIG. 6A is a sectional view illustrating a stage in a fabrication methodaccording to an embodiment of the invention subsequent to the stageillustrated in FIG. 5.

FIG. 6B is a fragmentary plan view of a wafer or portion of wafercorresponding to FIG. 6A.

FIG. 7 is a sectional view illustrating stacked microelectronic units inaccordance with an embodiment of the invention.

FIG. 8 is a sectional view illustrating a stacked microelectronic unitin accordance with a variation of the embodiment of the inventionillustrated in FIG. 7.

FIG. 9A is a sectional view a illustrating a stage in a fabricationmethod according to a variation of the embodiment of the inventionillustrated in FIG. 7.

FIG. 9B is a fragmentary partial plan view corresponding to thesectional view of FIG. 9A.

FIG. 10 is a sectional view illustrating a stacked microelectronic unitin accordance with a variation of the embodiment of the inventionillustrated in FIG. 7.

FIG. 11 is a sectional view illustrating a stacked microelectronic unitas attached to external elements in accordance with an embodiment of theinvention.

FIG. 12 is fragmentary partial plan view illustrating a stackedmicroelectronic unit in accordance with a variation of the embodiment ofthe invention illustrated in FIG. 7.

FIG. 13 is a sectional view illustrating a stage in a fabrication methodin accordance with a variation of the embodiment of the inventionillustrated in FIGS. 2A-7.

FIG. 14 is a sectional view illustrating a stage in a fabrication methodin accordance with an embodiment of the invention subsequent to thestage illustrated in FIG. 13.

FIG. 15 is a plan view illustrating a microelectronic element in afabrication method in accordance with a variation of the embodiment ofthe invention illustrated in FIGS. 13-14.

FIG. 16 is a plan view illustrating microelectronic elements in afabrication method in accordance with an embodiment of the invention.

FIGS. 17 through 26 are sectional views illustrating successive stagesin a fabrication method in accordance with an embodiment of theinvention.

DETAILED DESCRIPTION

FIGS. 1A-B illustrate an array, or a portion of an array ofmicroelectronic elements, such as may be provided on a semiconductorwafer. FIG. 1A is a top plan view of a wafer 10 or portion of a waferand includes a plurality of microelectronic elements 12, 12′ (twelveprime), and 12″ (twelve double prime), each microelectronic elementbeing shown as a rectangle. As seen in FIG. 1A, each microelectronicelement is positioned side by side and adjacent to one another. Thewafer can be in the shape of a circular wafer. Hereinafter, for ease ofreference, the wafer 10 or wafer portion is referred to as “wafer”. Thewafer 10 may include numerous rows of microelectronic elements 12aligned along an X-axis and a Y-axis. The wafer may include any numberof microelectronic elements, including as little as tow or as many as isdesirable. The microelectronic elements are formed integral with oneanother using semiconductor fabrication techniques. Each of themicroelectronic elements of the wafer is typically of the same type. Themicroelectronic elements can have memory function, logic or processorfunction or a combination of logic and processor functions, among otherpossible types. In a particular example, each of the microelectronicelements includes a flash memory. For example, each microelectronicelement can be a dedicated flash memory chip.

Wafer 10 in FIG. 1A has a top edge 15, a right edge 13, a left edge 11and a bottom edge 17. FIG. 1B is sectional view of wafer 10 taken alongline 1B (FIG. 1A), showing left edge 11 and right edge 13 of wafer 10.FIG. 1C also shows that each microelectronic element of wafer 10 alsohas a front face 14 and an oppositely-facing rear face 16. Note that inFIG. 1C, the front face 14 of wafer 10 has been turned over such that itfaces downward in the figure.

In FIG. 1A, three microelectronic elements 12, 12″, and 12′ areindividually called out in the middle row of the wafer 10. Withreference to microelectronic element 12 of FIG. 1A, each microelectronicelement has a first edge 18, a second edge 20, a third edge 19 and afourth edge 21. When microelectronic element 12 is still part of thearray of wafer 10, a first edge 18 of one microelectronic element 12abuts (or is attached to) second edge 20 of a second and adjacentmicroelectronic element 12. Similarly, a third edge 19 (FIG. 1A) of onemicroelectronic element 12 is attached to a fourth edge 21 of anadjacent microelectronic element. Thus, a microelectronic element 12″positioned in a middle row of the wafer portion 10 is bordered by anadjacent microelectronic element at all four edges, as shown in FIG. 1A.Each of first edge 18, second edge 20, third edge 19 and fourth edge 21extends from the front face 14 to the rear face 16 of themicroelectronic element 12, as illustrated in FIG. 1B.

Portions of wafer 10 where adjacent microelectronic elements contact oneanother form saw lanes or strips 23 and 25 where the wafer can be cutwithout damaging the individual microelectronic elements. For instance,as shown in FIG. 1B, second edge 20′ of microelectronic element 12′abuts first edge 18′ of microelectronic element 12″ and forms a saw lane23. Similarly, throughout the wafer 10, saw lanes 23 are located atpositions where microelectronic elements 12 abut one another.

With reference to microelectronic element 12″ of FIG. 1B, eachmicroelectronic element includes a plurality of contacts 22, 22′ or 22″exposed at the respective front face 14 of the microelectronic element12. The contacts 22 can be, for example, bond pads or lands of themicroelectronic elements as originally formed in a wafer fabricationfacility. Each microelectronic element of the uncut wafer 10 has adevice region 26 (area within dashed lines 27 (FIG. 1A) and within solidlines 27 (FIG. 1B)) in which active semiconductor devices and typicallyalso passive devices are disposed. Each microelectronic element alsoincludes a non-device region disposed beyond edges of the device region26 where no active semiconductor devices or passive devices aredisposed. Note that the bounded area of device region 26 is shown as thearea between solid lines 27 in FIG. 1B.

In one stacked assembly fabrication embodiment, an assembly including aplurality of stacked microelectronic elements is fabricated bysimultaneously processing a plurality of microelectronic elements enmasse. Moreover, processing can be carried out simultaneously as tomicroelectronic elements which are arranged in form of an array, similarto the processing of an original wafer containing such microelectronicelements.

FIGS. 2A-7 illustrate stages in a method of forming a package orassembly of stacked microelectronic elements in accordance with a firstfabrication embodiment. FIG. 2A is a sectional view illustrating a wafer10 or portion of a wafer, such wafer including a plurality ofmicroelectronic elements 12 attached together at saw lanes, of which sawlanes 23 are shown in FIG. 2A. Typically, the wafer 10 or wafer portionincludes an m×n array of chips (m, n each greater than one) as describedabove with respect to FIGS. 1A-B. The thickness 37 of the wafer 10between the wafer's front face 14 and the rear face 16 remote therefrom(FIG. 2B) is reduced from an original thickness 35 (FIG. 2A), such as bya polishing, lapping or grinding process applied to the rear face 16.

Referring to FIGS. 2B-C, after reducing the wafer thickness, the waferthen is separated into individual microelectronic elements 12 bysevering, e.g., sawing or scribing wafer 10 along the dicing lanes 23and 25 (FIG. 1A).

From the individual microelectronic elements obtained during this stage(FIG. 2B), selected ones 12 of the microelectronic elements, i.e., knowngood die, are attached at their front faces to an adhesive carrier 160(FIG. 3) or other carrier having an adhesive interface (not shown). FIG.2C represents determination of a known good die 12 a and a rejected die12 b, the rejected die being removed from further processing.

Selected ones of the individual microelectronic elements then areattached in form of an array to a carrier layer 160 (FIG. 3) for furtherprocessing. The array of selected microelectronic elements form a“reconstituted wafer” which then is available for processing accordingto wafer-level processing techniques. A pick-and-place tool can be used,for example, to place each microelectronic element 12 at the properposition on the carrier 160 to form a layer of microelectronic elementswhich make up a first reconstituted wafer 130 as shown in sectional viewin FIG. 3. As seen therein, the reconstituted wafer 110 includesindividual microelectronic elements 12 that were selected from themicroelectronic elements 12 obtained during the dicing (sawing) stage ofFIG. 2B. Individual microelectronic elements 12 are referred to as theknown good die, and are attached to the carrier 160, with the rear faceof each die facing the carrier 160.

An advantage of processing a reconstituted wafer rather than theoriginal wafer 10 is that the microelectronic elements that make up eachreconstituted wafer can be individually selected. When some of themicroelectronic elements of the original wafer are of known or suspectedmarginal or failing quality, they need not be processed intoreconstituted wafers. Rather, those microelectronic elements can be leftout of the reconstituted wafer such that the reconstituted wafercontains better quality microelectronic elements. Selection of themicroelectronic elements to go into the reconstituted wafer can be basedon various criteria of quality or expected quality. Microelectronicelements can be selected based of visual, mechanical or electricalinspection, for example. Alternatively, or in addition thereto,individual microelectronic elements can be selected based on thelocation of the microelectronic element within the original wafer 10,such as when the location of the microelectronic element on the wafercorrelates to the quality of the microelectronic element. In aparticular embodiment, microelectronic elements may in fact be testedelectrically before placing each one into position on the reconstitutedwafer. Whether the microelectronic elements are selected based onvisual, mechanical or electrical criteria or other criteria, themicroelectronic elements which are selected for inclusion in thereconstituted wafer can be referred to as “known good” microelectronicelements or “known good die”.

The microelectronic elements are attached to a carrier 160 asillustrated in FIG. 3 such that confronting edges 118 of adjacentmicroelectronic elements 12 are spaced apart by a spacing 110. Thespacing between adjacent microelectronic elements can be selected inaccordance with the requirements of the fabrication process. Therefore,spacings of several microns, tens of microns, or even one hundredmicrons or more may be utilized, depending upon the particular type ofdie and package to be made.

After attaching the microelectronic elements 12 to the carrier 160, afill layer 116 (FIG. 4A) is formed which fills spaces 114 of thereconstituted wafer 130 between adjacent microelectronic elements 12.The fill layer may also overlie the front faces 14 or portions of thefront faces of the microelectronic elements 12, as seen in FIGS. 4B-C.The fill layer can include a variety of materials. The fill layer mayinclude a dielectric material for providing isolation between themicroelectronic elements and conductors which may be connected thereto,such as described in the following. For example, the fill layer mayinclude one or more inorganic dielectric materials such as an oxide or anitride, such as, for example, include silicon dioxide, silicon nitrideor other dielectric compound of silicon such as SiCOH, among others.Alternatively, the fill layer may include an organic dielectric, amongwhich are various polymers such as epoxies, polyimide, thermoplastics,thermoset plastics, among others, or the fill layer may include acombination of inorganic and organic dielectric materials. The filllayer 116 may be applied by a spin-on, roller coat, screening orstenciling process, among others. When the fill layer 116 overlies thefront faces 14 of the microelectronic elements 12, its thickness can bereduced or unevenness (unplanarity) in the fill layer 116 can be reducedby a planarization process, if desired. A chemical or abrasive processor a process combining chemical and abrasive action such as chemicalmechanical polishing can be used for this purpose.

Thereafter, traces 24 (FIGS. 4A-C) are formed which extend outwardlyfrom each of the contacts 22 beyond at least some of the confrontingedges 118 of the microelectronic elements and which may also extendbeyond confronting edges 119 of individual microelectronic elements 12.If the fill layer 116 overlies the front faces 14, at least top faces ofthe contacts 22 on the microelectronic elements should be exposed priorto forming the traces 24. Traces 24 of adjacent microelectronic elements12 may meet at a location between the edges 118, 119 of the adjacentmicroelectronic elements. Such traces 24 may actually form a singletrace extending between adjacent contacts 22 of adjacent microelectronicelements 12. However, it is not required that the traces actuallycontact one another.

Subsequently, as illustrated in FIG. 5, additional microelectronicelements 12A are attached to the initial microelectronic elements 12with an adhesive layer 162 between them. In like manner as describedabove, the additional microelectronic elements 12A can be reduced inthickness and can be selected for quality before attaching them to thefirst reconstituted wafer 130. The adhesive layer 162 can include a dieattach adhesive. Optionally, the adhesive layer can be selected forproperties of compliancy, thermally conductivity, impermeability tomoisture or other contaminant, or a combination of such properties. Theadhesive layer 162 may be a flowable adhesive or tacky (partially cured)adhesive applied to overlie the front surfaces 14 of microelectronicelements, after which microelectronic elements 12A are attached to theadhesive layer, such as using a pick-and-place tool. Alternatively, theadhesive layer 162 may be deposited as a liquid onto a peelable backingor attached as a partially cured adhesive layer 162 to a peelablebacking, after which microelectronic elements 12A then are attached tothe adhesive layer. After removing the peelable backing, the adhesivelayer 162 can then be aligned and joined with the microelectronicelements 12 and fill layer 116 of the reconstituted wafer 130. Asillustrated in FIG. 5, the microelectronic elements 12A of the secondlevel can have the same width 26A as the width 26 of the microelectronicelements 12 of the first level. Subsequently, as illustrated in FIG. 6A,a fill layer 116A is applied to fill spaces between confronting edges ofadjacent microelectronic elements 12A to form a second reconstitutedwafer 130A. The fill layer 116A may overlie portions of the front faces14A of the microelectronic elements 12A, with the contacts 22A thereofexposed. Extension traces 24A are now formed which contact the contacts22A exposed at the front surfaces 14A of the second layer ofmicroelectronic elements 12A. Subsequently, a dielectric packaging layer71 can be formed to overlie the traces 24A, thus forming a dielectricinsulative layer overlying traces 24A of a stacked assembly 30 includingreconstituted wafers 130, 130A.

Subsequently, a plurality of channels 46 are cut into the stackedassembly. The channels 46 can be formed using a mechanical cuttinginstrument not shown in the figures. Examples of such a mechanicalcutting instrument can be found in U.S. Pat. Nos. 6,646,289 and6,972,480, the disclosures of which are hereby incorporated by referenceherein. Alternatively, a laser cutting technique can be used to form thechannels.

As seen in FIG. 6B, the channels 46, 46′ can be formed by mechanicallycutting or laser-forming gaps aligned with the dicing lanes 32, 32′ ofthe stacked assembly 30. Channels 46 extend between adjacentmicroelectronic elements 12A in an up-down layout direction (which canbe referred to as north-south directions, although there is norequirement or expectation that such directions match the compassdirections of true north and south). Channels 46 extend in a directionof north-south dicing lanes 32 of the stacked assembly. In addition,channels 46′ extend between adjacent microelectronic elements 12A in aleft-right layout direction (which can be referred to as west-eastdirections, although there is no requirement nor intention that suchdirections match the compass directions of true west and east). Channels46′ extend in a direction of west-east dicing lanes 32′ of the stackedassembly.

As seen in FIG. 6B, each channel 46, 46′ need not extend continuouslyalong the respective dicing lanes 32, 32′ of the stacked assembly.Rather, the channels can be interrupted by gaps 47 in directions alignedwith the dicing lanes. The gaps are areas in which the channels are notcut into the stacked assembly. Within the gaps, the fill layer fills thespace between the confronting edges of adjacent microelectronicelements. In the example shown in FIG. 6B, the gaps can occur nearcorners 49 of the microelectronic elements. Forming the channels withgaps along the length of the dicing lanes in this manner can provide forincreased mechanical strength of the stacked assembly 30 duringsubsequent processing because the fill layer remains intact within thegaps.

Alternatively, in a variation of that shown in FIG. 6B, the gaps can beomitted such that the channels 46, 46′ extend continuously along thelengths of the dicing lanes 32, 32′. IN such case, a single cut may beused to form a channel extending downwardly between adjacentmicroelectronic elements 12A and 12 of multiple levels of the stackedassembly. The channels 46 can be formed in alignment with dicing lanes32 (FIG. 4A) which run between the confronting edges 118 ofmicroelectronic elements and extend in a direction parallel to the edges118. Similarly, channels 46′ can be formed in alignment with dicinglanes 32′ which run between the confronting edges 119 of microelectronicelements and extend in a direction parallel to the edges 119. Thechannels 46, 46′ are formed with sufficient width such that traces 24Aand 24 are exposed at walls 48, 50 (FIG. 6A) of the channels.

As further illustrated in FIG. 6, the channels may be formed such thatthey do not extend entirely through the stacked assembly 30. Forexample, as shown in FIG. 6A, the microelectronic elements 12 of theinitial level remain attached to each other as the channels 46 do notextend through the carrier layer 160 to which they are attached.However, the channels 46 do extend far enough so as to expose the traces24 of the microelectronic elements 12 of the initial level. Similarly,the channels 46 extend through adhesive layer 162 connecting the initiallevel of microelectronic elements 12 with the second level 12A.Optionally, the channels may extend through a lower adhesive layer 161which connects microelectronic elements 12 to the carrier layer 160.Although the channels 46 are illustrated having inclined walls 48, 50,optionally, the walls may be straight, that is, parallel to each otherand oriented in a normal direction to the plane defined by the frontfaces 14 of the microelectronic elements 12.

Once the various channels 46, 46′ have been created in the stackedassembly 30, leads 66 (FIG. 7) may be formed on the walls of thechannels 46 or walls of both the channels 46 and 46′. The leads 66 maybe formed by any suitable metal deposition technique, for example, aprocess that includes sputtering or electroless plating,photolithography and electroplating. A three-dimensionalphotolithography process may be employed to define locations of theleads, such as is disclosed in commonly owned U.S. Pat. No. 5,716,759,the disclosure of which is hereby incorporated by reference herein. Theleads 66 extend along walls of the channels 46, and electrically contactthe traces 24, 24A of the microelectronic elements 12, 12A,respectively, at each level of the assembly 30.

In the embodiment illustrated in FIG. 7, the leads 66 extend beyond thewalls 48, 50 of channels 46 such that the leads extend along a topsurface 34 of the stacked assembly adjacent to a front face 14A ofmicroelectronic element 12A. A rear face 16A of that microelectronicelement 12A is oriented towards a rear surface 36 of the stackedassembly. The leads 66 may include ends 75 or pads remote from channels46 on which solder bumps 74 may be disposed. Each lead 66 canelectrically connect with both a trace 24 of a microelectronic element12 and a trace 24A of microelectronic element 12A, as a result of thosetraces 24, 24A being exposed and aligned along one line extending up anddown a given wall, e.g. wall 48 of the channel 46. Alternatively, eachlead 66 can electrically connect with only one of the traces 24, 24Aexposed at a wall 48 of the channel, e.g., wall 48. Such result may beobtained by positioning the traces 24, 24A in different planes whichoccur at different positions into and out of the sheet relative to theparticular section which is illustrated in FIG. 7. For example, theplane in which trace 24 is found as illustrated in FIG. 7 may be offsetfrom the plane in which trace 24A is found such that trace 24 is closerto the viewer of FIG. 7 when viewed in three dimensions. Lead 66, whichis aligned and connected with trace 24, is also offset from trace 24Aand not in contact with trace 24A. So although in a two-dimensionalview, the traces 24, 24A may appear to be attached to lead 66 in FIG. 7,only one may be actually attached to the lead.

As shown in FIG. 7, after the channels 46 and various conductiveelements including leads 66 are formed in the stacked assembly 30,individual packages 80 may be severed from the stacked assembly byseparating the carrier layer 160 from the stacked assembly and cuttingor breaking any material remaining between adjacent microelectronicelements, such as in gaps 47 (FIG. 6B) of the stacked assembly. In thisway, a plurality of stacked individual packages or units 80 result, witheach stacked individual unit 80 containing a plurality ofmicroelectronic elements stacked one upon another. As shown in FIG. 7,each unit 80 has two vertically stacked microelectronic elements 12, 12Atherein, the microelectronic elements being joined together throughadhesive layer 162. Greater or fewer numbers of vertically stackedmicroelectronic elements can be included in the package. The package iscapable of being externally interconnected to other elements by ends 75of leads overlying the top surface 34 of the unit.

In a variation of the above-described embodiment, the adhesive layer162A between microelectronic elements 12, 12A of adjacent reconstitutedwafers need not be continuous. Instead, openings can be provided in suchadhesive layer before attaching the microelectronic elements 12Athereto. Since the traces 24 of the microelectronic elements 12 of thefirst reconstituted wafer extend beyond edges 118, 119 of themicroelectronic elements 12, traces 24 can be accessible from abovethrough the openings in the adhesive layer 162. In one embodiment, theadhesive layer can include a partially cured, tacky adhesive havingopenings in axial alignment with the spaces between confronting edges118 of the microelectronic elements 12A. The openings may be pre-punchedprior to attaching the microelectronic elements 12A thereto.Alternatively, the openings may be formed after the adhesive layer 162is attached to microelectronic elements 12 or after the adhesive layer162 is attached to microelectronic elements 12A but before the adhesivelayer with the microelectronic elements 12A thereon are attached to theinitial layer of microelectronic elements 12.

In one variation of the above-described embodiment, a stacked assembly180 (FIG. 8) includes a bottom packaging layer 132, the bottom packaginglayer of which may include a portion of the carrier layer 160 (FIG. 6A).Thus, the bottom packaging layer 132 can be severed from the carrierlayer 160 during the cutting operation used to form the channels 46, 46′(FIGS. 6A-6B). An adhesive layer 161 such as described above may jointhe microelectronic element 12 with the bottom packaging layer 132. Inaddition, the unit shown in FIG. 8 is capable of being externallyinterconnected by bottom unit contacts 176 exposed at the bottom surface134 of the unit. Bottom unit contacts 176, 176′ can be formed integrallywith leads 166, 166′, respectively, which connect with leads 66 at edges48, 50 of the unit. Leads 166, 166′ can be formed by processes similarto those described with reference to FIG. 7 above for the formation ofleads 66. For example, leads 166 can be formed through use of one ormore photolithography steps performed either before performing one ormore photolithography steps needed to form leads 166, 166′ or subsequentthereto. Alternatively, the carrier layer 160 (FIG. 6A) can includeleads 166, 166′ pre-formed thereon, such that when the leads 66 shown inFIG. 8 are formed, conductive connections are made between the leads 66and leads 166, 166′.

As in the above-described embodiment, each bottom unit contact 176, 176′may be connected to only one trace 24, 24′, respectively of onemicroelectronic element. Alternatively, each bottom unit contact 176 maybe connected to two traces 24, 24A which are aligned together within theplane in the section illustrated in FIG. 8. Similarly, each bottom unitcontact 176′ may be connected to two traces 24′, 24A′ which are alignedtogether. The units illustrated in FIGS. 7 and 8 show microelectronicelements stacked only two high in the vertical direction (the directionextending normal to the front surfaces of the microelectronic elements).However, each unit can include a greater number of vertically stackedmicroelectronic elements such that the microelectronic elements can bevertically stacked three high, four high or a greater number.

In a variation (FIG. 9A) of the above-described process of formingstacked packages, microelectronic elements of differing sizes are joinedtogether within a stacked assembly 230. FIG. 9A illustrates a stage offabrication prior to that in which channels 46 (FIGS. 6A-B) are formed.FIG. 9B is a fragmentary plan view corresponding thereto, lookingtowards front faces of microelectronic elements 212A, 212A′. Asillustrated in FIGS. 9A-B, some of the microelectronic elements 212Awhich make up a second level 232A of the stacked assembly 230 may havegreater or smaller dimensions than microelectronic elements 212, 212′ ofa lower level or initial level 232 therein. In one example,microelectronic element 212′ of the initial level 232 can have smallerdimensions than a microelectronic element 212A′ of the second level. Inanother example, microelectronic element 212 of the initial level 232can have larger dimensions than microelectronic element 212A.

Thus, as seen in plan in FIG. 9B, both the length 234A and width 236A ofthe front face of the upper microelectronic element 212A are smallerthan the length 234 and width 236 of the front face of the lowermicroelectronic element 212 to which the upper microelectronic element212A is vertically aligned. In another example illustrated in FIG. 9A,the width 236A′ of the microelectronic element 212A′ is greater than thewidth 236′ of microelectronic element 212′ of the lower level. Theversatility of the techniques described herein is exemplified by thestructure shown in FIGS. 9A-B. Specifically, traces 224 and 224A of eachlevel can be of different lengths, since the process of forming filllayers 220, 220A between edges of microelectronic elements leaves asurface on which traces of different lengths can be formed by subsequentprocessing, as described above with reference to FIG. 4. Many variationscan be made whereby, for example, microelectronic elements of an upperlayer have larger size than those of the lower layer. In yet anotherexample, smaller dimensioned microelectronic elements can be verticallysandwiched between larger dimensioned chips, or larger dimensioned chipscan be vertically sandwiched between smaller dimensioned chips. FIG. 10illustrates a stacked microelectronic unit 280, formed by furtherprocessing the stacked assembly in a manner as described above withrespect to FIGS. 6A-B and 7.

An individual stacked microelectronic unit 80 or package (FIG. 11) canbe electrically connected via solder bumps 74 at the front face 89 ofthe package 80 to an interconnection element 90, e.g., a dielectricelement, substrate, circuit panel or other element having terminals 84,86 and conductive wiring therein. One or more additional microelectronicelements 70 can be attached to a rear face 88 of the package 80 andelectrically interconnected by bond wires 82 to the terminals 84 of theinterconnection element. Such microelectronic element 70 can include oneor more additional microelectronic elements that supplement the functionof the stacked package 80, e.g., such as a microcontroller, or caninclude one or more redundancy elements for substitution with one ormore microelectronic elements 12, 12A, 12B, etc. of the assembly in caseof a problem with such microelectronic element. In a particularembodiment, the individual stacked assembly or unit 80 may beincorporated into microprocessors, and RF units among other assemblies.One or more stacked units 80 may incorporate particular types ofmicroelectronic elements such as flash memory or dynamic random accessmemory (DRAM) units and be incorporated in various units includingmemory modules, memory cards, and the like. Other exemplary arrangementsfor mounting and interconnecting the stacked unit 80 to aninterconnection element are shown and described in commonly owned U.S.patent application Ser. No. 11/787,209 filed Apr. 13, 2007, thedisclosure of which is hereby incorporated herein by reference. Forexample, the stacked unit 80 can be mounted with the front face facingeither downwardly towards the interconnection element or upwardly awaytherefrom. In addition, the one or more additional microelectronicelements can be mounted either face-up as shown in FIG. 11 or face-down,such that the contact-bearing face is flip-chip mounted to the stackedunit 80. Various combinations and configurations and possible, such asillustrated in incorporated U.S. patent application Ser. No. 11/787,209.

FIG. 12 is a fragmentary partial plan view showing a variation of theabove embodiment, wherein, after forming the stacked assembly 30 (FIG.5), the step of forming channels which expose all of the traces 24, 24Aof the stacked microelectronic elements 12, 12A is omitted. Instead, aseries of individual openings 228 are formed between the edges ofrespective microelectronic elements in alignment with the streets 218,220. Unlike the channels 46, 46′ (FIGS. 6A-B) formed according to theabove-described embodiment, each of the openings 228 exposes no morethan a single trace 224 of each respective microelectronic element. Asshown in FIG. 12, traces 224 connected to contacts of two adjacentmicroelectronic elements 212 are exposed within one of the openings 228between two adjacent microelectronic elements. In the stacked assembly30 as shown in FIG. 12, a plurality of traces 224 connected tomicroelectronic elements of the same subassembly can be exposed within asingle opening 228. Alternatively or in addition thereto, a plurality oftraces 224 can be connected to the microelectronic elements ofrespective reconstituted wafers 130, 130A (FIG. 7) at first and secondlevels of the stacked assembly. However, openings 228 can be formed suchthat no more than one trace of each individual microelectronic elementis exposed within each opening 228.

To form leads and external unit contacts connected to individual ones ofthe traces 224 all openings 228 in the stacked assembly can besimultaneously filled with a conductive material to form conductive viasconnected to single traces of each microelectronic element. For example,the openings can be filled with a metal to form conductive vias bydepositing a primary metal, e.g., by sputtering or electrolessdeposition, and then electroplating the resulting structure. Some of themetal deposited by the electroplating step may form a layer overlyingthe packaging layer 71 (FIG. 6A) above the front faces 14A of themicroelectronic elements 12A. Such metal layer can be removed fromoverlying the front faces of the microelectronic elements, leavingsurfaces of individual conductive vias exposed within each opening 228.Alternatively, the metal layer overlying the front faces of themicroelectronic elements 212A can be patterned by photolithography intoindividual leads extending from the vias onto locations overlying thefront faces of microelectronic elements 212A, similar to the leads 66overlying the packaging layer 34 above the front faces 34 ofmicroelectronic elements 12A in FIG. 7. Conductive bumps, e.g., solderbumps are balls, may then be formed at ends of the leads, as shown anddescribed above with reference to FIG. 7.

In a particular embodiment, the process of forming the leads can beadditive; the leads can be formed by printing the metal compositethrough a screen or stencil onto the stacked assembly. For example, ametal composite can be deposited through a stencil or by screen-printingto fill the openings 228 in the stacked assembly and form the leads 66.Subsequently, the stacked assembly can be heated to cure the metalcomposite. The openings can be filled at the same time by the samedeposition process as that which forms the leads or the openings can befilled at a different time or different process than that which formsthe leads. The metal composite can include, for example, a metal-filledpaste such as an epoxy-solder composition, silver-filled paste, or otherflowable composition having a dielectric, e.g., polymeric componentloaded with metal particles.

In a variation of the embodiment described above (FIGS. 2-7), FIGS. 13and 14 illustrate a method of forming stacked microelectronic units.Referring to FIG. 13, an array of microelectronic elements 312 at afirst level are bonded to a carrier layer 360 and processed to form afill layer 316 and traces 324 so as to form a reconstituted wafer 310 ata first level, and such that an edge 340 of a microelectronic elementtherein occurs at a lateral position 350. Subsequently, an array ofmicroelectronic elements 312A are bonded to the reconstituted wafer 310and processed to form a corresponding fill layer and traces 32A so as toform a second reconstituted wafer 310A at a second level. An edge 340Aof a corresponding overlying microelectronic element of the secondreconstituted wafer 310A occurs at a different position 350A which isoffset in a lateral direction 320 from the edge 340 of the first wafer310. Thus, for the microelectronic element 312A of the secondreconstituted wafer having an area overlapping an area of themicroelectronic element 312 to which it is bonded, the edge 340A of themicroelectronic element 312A is displaced in the lateral direction 310from the edge 340 of the underlying microelectronic element 312. Anexemplary distance of the lateral offset between edges of verticallyadjacent overlapping microelectronic elements can range from a fewmicrons to tens of microns or more. These steps are repeated to attachmicroelectronic elements 312B to form a third reconstituted wafer 310Bhaving edges offset from the edges of underlying microelectronicelements 312A and to form a fourth reconstituted wafer 310C containingmicroelectronic elements 312C to form the stacked assembly 330 shown inFIG. 13.

An advantage of forming the stacked assembly in this manner is thatprocess tolerances can improve for forming leads 366 (FIG. 14) adjacentto exposed edges 340, 340A, 340B and 340C. The lateral displacement ofeach succeeding overlapping microelectronic element in the stackedassembly allows for slope in the walls 370, 372 of the channel 346formed therein. Lateral displacement of the edge (e.g., edge 340A) ofeach microelectronic element with respect to the edge (e.g., edge 340)of each microelectronic element immediately below it allows the walls370, 372 of the channel 346 to be more heavily sloped, i.e., at agreater angle from the vertical. Here, “vertical” is defined as a normalangle to the plane defined by the contact-bearing surface 314 of amicroelectronic element, e.g., element 312. With the slope in wall 370,the process of forming channels, e.g., by cutting or laser drilling(FIGS. 6A-B) exposes traces 324 at edges 340, even when the length ofsuch traces 324 is limited.

It is apparent that edges 342, 342A, 342B, 342C of microelectronicelements which are adjacent to wall 372 of the channel 346 are alsolaterally offset. Again, these edges are displaced in direction 320 fromeach adjacent microelectronic element immediately below it. However, inthis case, edges 342 are displaced in a direction which is opposite fromthe direction in which the wall 372 is sloped. Accordingly, there are notraces connected to leads at such edges 342.

FIG. 16 is a plan view illustrating a microelectronic element 312 of onereconstituted wafer 310 of a stacked assembly in a variation of theabove-described embodiment (FIG. 15). When the microelectronic elements312 are provided with contact pads adjacent to edges 340 and 342 asillustrated in FIG. 15, a redistribution layer including additionaltraces 326 can be provided which extends between the pads at edge 342and outwardly beyond a third edge 344 of the microelectronic element312. When forming the stacked assembly 330 (FIG. 13), overlappingmicroelectronic elements of each successively stacked wafer 310 can beoffset as well in a direction 362. In this way, leads can be formed inchannels which expose traces 328 along the third edges 344 of theoverlapping microelectronic elements, and process tolerance can also beimproved for forming such leads.

In a particular variation of the above-described embodiments, alignmentfeatures 560, 562 (FIG. 16) can be formed on the front face 517 of eachmicroelectronic element 512 at a stage of fabrication when the outwardlyextending traces 524 are formed. The alignment features can be formed ofmetal simultaneously with the traces 524 by the same processing whichforms the traces, such processing illustrated and described above withrespect to FIGS. 4A-C. Alternatively, the alignment features can beformed by different processing from that which forms the traces. Statedanother way, the alignment features can be formed using all the sameprocessing steps as used to form the traces or by performing at leastone processing step different from the processing steps used to form theredistribution traces.

When the alignment features are formed by different processing, they mayinclude a material which is not included in the traces 524. Likewise,traces 524 may include a material, e.g., a metal which is not includedin the alignment features. Optionally, the alignment features may beformed to include a material which is particularly reflective of awavelength of a source, e.g., an infrared source used to illuminate thealignment features.

The alignment features may include two or more types of features, e.g.,closed features 560 and open features 562 to permit edges of eachmicroelectronic element 512 to be distinguished and to facilitatealignment of each microelectronic subassembly within two dimensions. Thealignment features 560, 562 may be aligned with the area of eachunderlying microelectronic element 512 such that the alignment featuresdo not extend beyond the edges of each microelectronic element 512.Alternatively, some or all alignment features, e.g., feature 560′ may beonly partially aligned with the area of the microelectronic element 512,such that the alignment feature extends beyond an edge of themicroelectronic element 512. In another variation, as shown with respectto microelectronic element 512′, alignment features 560″ and 562″ aredisposed at locations which lie beyond the edges 518′, 519′ of themicroelectronic element 512′. Such alignment features 560″, 562″ may bealigned entirely or partially with the area that the later formedchannels 46 (FIGS. 6A-B) will occupy. In this way, alignment featurescan be provided while at the same time permitting a compact layout to beachieved in the microelectronic elements.

The alignment features 560, 562 at the front face 517 of an initiallevel 130 (FIG. 5) of a stacked assembly may be illuminated and detectedby instruments disposed above that level 130 and assembling elementsthereto to form the next level of microelectronic elements 130A (FIG. 5)such as described above with reference to FIG. 7. Alternatively or inaddition thereto, the alignment features 560, 562 at the front face 517of the first microelectronic subassembly 130 and of the secondmicroelectronic assembly 130A may be illuminated and detected byinstruments disposed below the carrier layer 160 (FIG. 5). In such case,the carrier layer 160 should have optical transmission characteristicsthat permit sufficient illumination by light passing through thethickness of the carrier layer 160.

FIGS. 17 through 20 are partial sectional views illustrating stages in aprocess of forming a reconstituted wafer 630 (FIG. 20), which can bedefined as a subassembly including a single layer of semiconductor dieor microelectronic elements arranged in an array. Such reconstitutedwafer 630, representing a subassembly, can be utilized to make a stackedassembly including a plurality of subassemblies. The reconstituted wafer630 has structure similar to that of a level 130 of the stacked assemblyas shown and described above with respect to FIGS. 4-5. Thereconstituted wafer 630 can be stacked and joined together withadditional reconstituted wafers 630 to form a stacked assembly 30 (FIG.6A) and further processed into a stacked microelectronic unit 80 asshown in FIG. 7.

FIG. 17 illustrates a stage of fabrication in which a microelectronicelement 612, e.g., a “known good die” is joined with its front face 614oriented in a downward direction to a temporary carrier layer 660 with adielectric layer 662 filling a space between the front face 614 and thecarrier layer 660. As in the above-described embodiment, a plurality ofmicroelectronic elements arranged in an array are placed and joined inthis manner to the carrier layer 660. The dielectric layer can includeor consist essentially of an adhesive or other dielectric joiningmaterial such as described above with reference to FIGS. 3 through 5,e.g, a passivation fill, which can have an organic component, inorganiccomponent, or both. In one example, the dielectric layer includes apassivation layer 662 adjacent to the front face of the die, thepassivation layer being removably attached to the carrier layer via atemporary adhesive.

Subsequently, as illustrated in FIG. 18, a dielectric fill material 664is deposited to fill gaps between the die 612 and other die, which arenot shown but are attached to the carrier layer 660 and arranged withthe die 612 in form of an array. The dielectric fill 664 can include thesame dielectric material or other material as that of the layer 662. Thedielectric fill 664 may coat the rear surfaces 616 of the dies or mayonly abut or partially cover the rear surfaces. The dielectric fill maybe applied as a flowable self-planarizing material such as a spin-ondielectric composition or may be roller-coated or screened or stenciledinto place using an appropriate applicator, among many possibleexamples. The dielectric material may then be cured by baking or otherappropriate post-deposition treatment.

Subsequently, as illustrated in FIG. 19, the die of the resultingreconstituted wafer 630 can be can be subjected to polishing, grindingor lapping from the rear surface 616 until the thickness 625 reaches adesired value. The thickness of the die typically is measured as thedistance between front and rear surfaces 614, 616. The carrier layer 660provides mechanical support and rigidity to protect the die of thereconstituted wafer from shear stresses which could lead to warping,twisting, cracking or breaking. The dielectric fill layer 664 also helpspreserve the structural integrity of the die during the grindingprocess. A final die thickness which can be very small, such as a fewmicrons, e.g., 5 microns, can be achieved in this way. Of course, thethickness of the die can be reduced to greater values, as required for aparticular type of die or package. Thus, the die thickness can bereduced to a value of 15 microns or below, or alternatively, may bereduced to a few tens of microns.

Referring to FIG. 20, after reducing the thickness, the reconstitutedwafer 630 including the dielectric fill layer 664, the die 612 and thepassivation layer 662 thereon can be detached from the carrier layer 660to free the reconstituted wafer 630 from the carrier layer. In contrastto that shown in FIG. 19, in the view shown in FIG. 20, the die 612 ofthe reconstituted wafer 630 has the front face 614 oriented in an upwarddirection. Subsequently, openings 615 are made in the passivation layer662 in alignment conductive pads 622, e.g., bond pads of the die, thusexposing conductive surfaces of the bond pads. Conductive traces 624 canthen be formed in contact with the exposed bond pads 622, each trace 624extending over the dielectric layer 662 outwardly beyond an edge 640 ofeach die 612. Thus, traces 624 extend along a surface of a dielectriclayer 662 at a front surface 654 of a reconstituted wafer 630. A rearface 616 of a microelectronic element 612 can be exposed at a rearsurface 656 of the reconstituted wafer.

In the stage of processing illustrated in FIG. 21, a secondreconstituted wafer 630A, fabricated in accordance with the methodillustrated in FIGS. 17-19, is shown with the rear face 616A of a die612A therein facing down and away from the carrier layer 660A. Asillustrated in FIG. 21, the front face 614A of the die 612A remainsattached to a carrier layer 660A used in fabricating the secondreconstituted wafer 630A. Another reconstituted wafer 630 can then beattached to the second reconstituted wafer 630A such that the traces 624of the reconstituted wafer 630 are adjacent to rear faces 616A of themicroelectronic elements 612A in the second reconstituted wafer 630A. Asshown in FIG. 21, edges 640, 640A of the microelectronic elements 612,612A of the respective reconstituted wafers 630, 630A can be alignedalong a vertical line 634 normal to the front face 616A. Subsequently,the carrier layer 660A is detached from the second reconstituted wafer630A, and second layer traces 624A connected to pads 622A of die 612Aare formed by the above-described process (FIG. 20), resulting in thestacked assembly 600 illustrated in FIG. 22.

A third reconstituted wafer 630B, fabricated in accordance with theabove-described process (FIGS. 17-19), is illustrated in FIG. 23, havingcarrier layer 660B attached. The third reconstituted wafer 630B can bealigned and joined to the second reconstituted wafer of the stackedassembly 600 in similar manner to that described above (FIG. 21). FIG.24 illustrates the resulting stacked assembly 600′, after the carrierlayer 660B is removed and traces 624B are formed by the above-describedprocess (FIG. 20).

Additional layers of reconstituted wafers can be aligned and joined withthe stacked assembly 600′ by the above-described processing to form astacked assembly having a greater number of layers. For example, FIG. 25illustrates a stacked assembly 600″ which includes four levels ofreconstituted wafers 630, 630A, 630B and 630C therein. A cutting tool670, e.g., a mechanical instrument or laser, is shown above a line 632where a channel is to be formed in the stacked assembly 600″. Channelshaving inclined or straight vertical walls typically are formed betweenconfronting edges of adjacent microelectronic elements of eachreconstituted wafer, as shown and described above with respect to FIGS.6A-B. Channels can also be formed at edges of the stacked assembly whereedges of microelectronic elements are adjacent only to one wall of thechannel.

FIG. 26 illustrates the stacked assembly 600″ after formation of a notch646. Traces 624C and leads 666 connected to other traces 624, 624A, 624Bof the stack can be formed either by separate processing or by acombined process, similar to that described above with reference to FIG.7.

In variations of the embodiments illustrated in FIGS. 17 through 26,edges of the semiconductor die or microelectronic elements in thestacked assembly can be deliberately displaced from each other, as shownand described above with reference to FIGS. 9A-B, 10 or FIGS. 13-15. Ina particular variation, traces of each semiconductor die ormicroelectronic element can be connected in a manner as described abovewith reference to FIG. 12. Alignment features can be fabricated on eachdie as illustrated and described above with respect to FIG. 16.

Features of the various embodiments described herein can be combined toform microelectronic units having some or all of the features of onedescribed embodiment and one or more features of another describedembodiment. Applicants intend by this disclosure to permit all suchcombination of features, even though such combinations may not beexpressly described.

Although the invention herein has been described with reference toparticular embodiments, it is to be understood that these embodimentsare merely illustrative of the principles and applications of thepresent invention. It is therefore to be understood that numerousmodifications may be made to the illustrative embodiments and that otherarrangements may be devised without departing from the spirit and scopeof the present invention as defined by the appended claims.

1. A method of fabricating a stacked microelectronic assembly,comprising: a) providing first and second subassemblies, eachsubassembly having a front surface and a rear surface remote from thefront surface, each subassembly including a plurality of spaced apartmicroelectronic elements having front faces and contacts adjacent to thefront surface, rear faces adjacent to the rear surface, and edgesextending between the front and rear faces; b) forming a plurality oftraces at the front surface of the first subassembly, the tracesextending from the contacts of the first subassembly to beyond the edgesof the microelectronic elements of the first subassembly; c) joining thefirst and second subassemblies such that the rear surface of the secondsubassembly confronts the front surface of the first subassembly; d)forming a plurality of traces at the front surface of the secondsubassembly, the traces extending from the contacts of the secondsubassembly to beyond the edges of the microelectronic elements of thesecond subassembly; and e) forming leads in at least one openingextending between edges of adjacent microelectronic elements of thefirst and second subassemblies, the leads being connected to the tracesof the microelectronic elements of the first and second subassemblies.2. A method as claimed in claim 1, wherein each of the microelectronicelements of the first and second subassemblies has a thickness of lessthan about 50 microns between the front face and the rear face.
 3. Amethod as claimed in claim 1, wherein at least one of themicroelectronic elements includes flash memory.
 4. A method of making astacked microelectronic unit including the method as claimed in claim 1,further comprising, after step (e), severing the stacked microelectronicassembly between edges of adjacent microelectronic elements into aplurality of stacked microelectronic units, each unit includingmicroelectronic elements from each of the first and second subassembliesand leads connected to traces of the microelectronic elements.
 5. Amethod as claimed in claim 1, wherein the at least one opening includeschannels extending between confronting edges of adjacent microelectronicelements.
 6. A method as claimed in claim 4, wherein the at least oneopening includes a plurality of spaced apart openings aligned with edgesof the microelectronic elements and leads of each stackedmicroelectronic unit extend within respective individual ones of thespaced apart openings, each lead being conductively connected with asingle one of the traces.
 7. A method as claimed in claim 1, wherein thefront face of a given microelectronic element of the second subassemblyhas at least one dimension different from a corresponding dimension ofthe front face of a microelectronic element of the first subassemblythat the front face of the given microelectronic element overlies.
 8. Amethod as claimed in claim 1, wherein a front face of a givenmicroelectronic element of the first subassembly has at least onedimension different from a corresponding dimension of a front face ofanother microelectronic element of the first subassembly.
 9. A method asclaimed in claim 8, wherein a front face of a given microelectronicelement within the stacked assembly has at least substantially the samedimensions as a front face of another microelectronic element that thegiven microelectronic element overlies within the stacked assembly. 10.A method as claimed in claim 1, wherein each subassembly furtherincludes alignment features adjacent to the front surface, the alignmentfeatures and the traces being elements of a metal layer exposed at thefront surface.
 11. A method as claimed in claim 1, wherein step (c)includes joining the second subassembly to the first subassembly suchthat edges of microelectronic elements of the second subassembly aredisplaced in a lateral direction relative to edges of microelectronicelements of the first subassembly in vertical alignment therewith, andthe opening formed in step (e) has a sloped wall exposing the tracesadjacent to the laterally displaced edges of the vertically stackedmicroelectronic elements.
 12. A method as claimed in claim 11, whereinthe lateral direction is a first lateral direction, the edges of eachmicroelectronic element include first edges and second edges transverseto the first edges, and step (c) includes joining the second subassemblyto the first subassembly such that second edges of microelectronicelements of the second subassembly are further displaced in a secondlateral direction relative to second edges of microelectronic elementsof the first subassembly in vertical alignment therewith, the secondlateral direction being transverse to the first lateral direction, themethod further comprising forming a second opening having a sloped wallexposing second traces adjacent to the second edges, and forming leadsconnected to the second traces.
 13. A stacked microelectronic unit, thestacked unit having a top surface and a bottom surface remote from thetop surface, the stacked unit comprising: a plurality of verticallystacked microelectronic elements including at least one microelectronicelement having a front face adjacent to the top surface and having arear face oriented towards the bottom surface, each of themicroelectronic elements having traces extending from contacts at thefront face beyond edges of the microelectronic element; a dielectriclayer contacting the edges of the microelectronic elements andunderlying the rear face of the at least one microelectronic element;leads connected to the traces extending along the dielectric layer; andunit contacts connected to the leads, the unit contacts being exposed atthe top surface.
 14. A microelectronic stacked unit as claimed in claim13, further comprising at least some bottom unit contacts exposed at thebottom surface, the bottom unit contacts being connected to the contactsof at least one of the microelectronic elements.
 15. A stackedmicroelectronic unit, comprising: a first microelectronic element havinga front face bounded by a first edge and a second edge remote from thefirst edge; a second microelectronic element having a front face boundedby a first edge and a second edge remote from the first edge, whereinthe first edge of the second microelectronic element overlies the frontface of the first microelectronic element and the first edge of thefirst microelectronic element extends beyond the first edge of thesecond microelectronic element; a dielectric layer overlying the firstedges of the first and second microelectronic elements, the dielectriclayer defining an edge of the stacked unit; and leads connected totraces at the front faces of the first and second microelectronicelements, the leads extending along the edge of the stacked unit.
 16. Astacked microelectronic unit as claimed in claim 15, wherein the firstand second microelectronic elements include third edges oriented in adirection transverse to the first edges, wherein the third edge of thesecond microelectronic element overlies the front face of the firstmicroelectronic element and the third edge of the first microelectronicelement extends beyond the third edge of the second microelectronicelement, the dielectric layer defines a second edge of the stacked unitoverlying the third edges of the microelectronic elements, and thestacked unit further includes second leads extending along the secondedge of the stacked unit.
 17. A stacked microelectronic unit,comprising: a first microelectronic element having a front face boundedby a first edge and a second edge remote from the first edge; a secondmicroelectronic element having a front face bounded by a first edge anda second edge remote from the first edge, wherein the front face of thesecond microelectronic element overlies the front face of the firstmicroelectronic element and the front faces of the first and secondmicroelectronic elements differ in at least one of length along thefront faces in a longitudinal direction or in width along the frontfaces in a lateral direction transverse to the longitudinal direction; adielectric layer overlying the first edges of the first and secondmicroelectronic elements, the dielectric layer defining an edge of thestacked unit; and leads connected to traces at front faces of themicroelectronic elements, the leads extending along the edge of thestacked unit.